1. Field of the Disclosure
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming an epi semiconductor material in trenches formed above a semiconductor device and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically includes doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. The gate structures for both planar and FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap F. The gate structure D typically includes of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D is the channel region of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size.
In some cases, damage to the fin structures in the source/drain regions of the device may not be a significant concern, i.e., an application in which there may be significant growth of epi material in the source/drain regions. Nevertheless, even in those situations, problems can occur if too much of the epi material is grown in the source/drain regions of the device; e.g., epi-to-epi shorting between adjacent devices or around the end of the gate structure on a single device.
Another area of potential concern is related to the formation of so-called self-aligned contacts. The typical process flow for forming such contacts involves forming an opening in a layer of silicon dioxide that is supposed to stop on a silicon nitride gate cap layer and a silicon nitride sidewall spacer (that are formed to protect the gate materials). Unfortunately, there is a risk of consuming too much of the gate cap layer and/or the sidewall spacer during the contact opening etching process which can lead to exposure of the gate materials. When the contact is formed in the contact opening, there is a chance of creating a contact-to-gate electrical short due to the loss of the cap and/or spacer material.
FIG. 1B is a simplistic plan view of an illustrative transistor device (which can be either a planar or FinFET device). As depicted, the transistor includes source and drain regions that are formed in an active region surrounded by isolation material, typically silicon dioxide. The gate structure (“gate”) of the device is formed above the active region and one or more sidewall spacers are formed adjacent the gate structure using a variety of known processing techniques. Typically the spacers are formed by conformably depositing a layer of spacer material, e.g., silicon nitride, and thereafter performing an anisotropic etching process. Note that the spacer is formed around the entire perimeter of the gate structure and that the spacer is formed with the intent that it has a substantially uniform thickness at all locations around the perimeter of the gate structure.
Unfortunately, as device dimensions have decreased and packing densities have increased, the formation of epi semiconductor material in the source/drain regions of the device may lead to several problems. For example, since the epi material tends to grow in both the vertical and lateral directions (albeit sometimes not at the same rate in each direction), there is a chance that some of the epi material may form in regions where it should not be located. The extent and amount of undesirable epi semiconductor material formation will vary depending upon the particular application and the quality of the manufacturing processes used to manufacture the device. In a worst case scenario, this undesirable epi semiconductor material may form around the entire end surface of a particular gate electrode so as to effectively from a conductive “bridge” between one or both of the source/drain regions and the gate electrode. In another example, such undesirable epi semiconductor material may span the space between the opposing end surfaces of two spaced-apart gate electrode structures, wherein the epi material may form on one or both of the spaced-apart gate structures. In another example, the epi semiconductor material may bridge the space between spaced-apart active regions and contact other epi material formed on the adjacent device. As a result of such undesirable and unpredictable epi formation, the resulting semiconductor devices and the integrated circuits including such devices may completely fail or operate at less than acceptable performance levels.
One solution that manufacturers have adopted to try to limit such problems with epi material growth is to limit the thickness or height of the epi semiconductor material. However, this proposed remedy has several drawbacks. First, limiting the thickness of the epi material necessarily reduces the total volume of the epi material that is formed. Metal silicide regions are typically formed on such epi material to reduce the contact resistance for a contact that is to be formed to contact the source/drain regions. During the metal silicide formation process, some of the epi material is consumed. Thus, limiting the thickness of the epi material can lead to a situation where very little of the epi material is left after the metal silicide regions are formed. This can position the bottom of the metal silicide region very near the upper surface of the substrate or fin, which can undesirably increase the contact resistance.
Additionally, there are inherent issues with the prior art techniques used to form epi material on the source/drain regions. For example, in one prior art process flow, spacers are formed adjacent a gate structure, a layer of oxide material is formed between adjacent gate structures and a CMP process is performed on the oxide material. Thereafter, an etching process is performed on the oxide material to expose the source/drain regions between the gate electrodes. Unfortunately, the spacers are exposed to this contact etch process which can lead to undesirable amounts of spacer material loss and possible exposure of the gate structure. On the other hand, if the oxide material is formed before the spacers are formed adjacent the gate structure, so as to avoid damage to the spacers, other problems are presented. First, there is potential damage to the gate structure when the contact opening is formed since it is not protected by a spacer. Second, if a spacer is formed after the contact opening is formed, there is no protection for the gate structure in the areas that do not correspond to the contact opening. Thus, there would be a high likelihood of exposing portions of the unprotected gate structures during subsequent processing and potentially creating short circuits. One possible remedy to avoid the potential formation of such undesirable epi material would be to simply increase spacing between devices and increase gate pitches. However, such a “solution” would lead to reduced packing densities, which is counter to the ongoing trend in the industry now and for the foreseeable future.
The present disclosure is directed to various methods of forming an epi semiconductor material in trenches formed above a semiconductor device and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.